MINIMIZING THE FIR FILTER AREA USED IN A FPGA POWER COMPUTING INSTRUMENT

Autor/autori: Lecturer Eng. Catalin DAMIAN, PhD, Assoc. Prof. Eng. Cristian ZET PhD, Assist. Prof. Eng. Elena DANILA

Rezumat: Partea de instrumentatie ocupa un loc important in orice domeniu. Lucrarea prezinta un instrument pentru masurarea simultana a puterii active, reactive si aparente implementat pe un circuit de tip arie logica programabila. Implementarea fara optimizare a acestui instrument ocupa aproximativ 76% dintr-o arie logica de tip FLEX10K. Pentru a micsora spatiul ocupat se incearca o optimizare a blocurilor de filtrare. Metoda propusa se bazeaza pe scrierea coeficientilor filtrelor ca suma de puteri ale lui doi. Se obtine astfel o micsorare cu 10 % a spatiului total ocupat.

Cuvinte cheie: instrumentatie, arii logice, filtrare, calcul puteri


Abstract: Instrumentation is essential in any domain. The paper presents an instrument for simultaneous active, reactive and apparent power measurement. The instrument is implemented on a field programmable gate array (FPGA) device. The instrument is fitting on 76% of total area of a FELX10K device if implemented without any optimization algorithm. To minimize the occupied area, an optimization for the filtering blocks is performed. The method consists in coding the filtering coefficients like sum-of-power-of-two (SOPOT) terms. The total area is with 10% less than the initial case.

Keywords: instrumentation, FPGA, FIR filtering, power computing

 

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